1. Field of the Invention
The present invention relates generally to techniques for managing external memory utilized in processors (or CPU, for Central Processing Unit) and, more specifically, it concerns a buffer of memory pages, also called a Translation Look-aside Buffer (TLB).
2. Description of the Related Art
Transition Look-aside buffers (TLB) exist in processors using the concept of paged virtual memory. This is a hardware element that functions as a cache for the latest address translations used by the processor to access data stored in external memory when the processor is executing one or more application programs.
For this purpose, a TLB includes a given number N of lines or entries (Entry) for storing N respective address translations, each associating a given Virtual Page Number (or VPN) with a given Physical Page Number (or PPN). The virtual addresses are the only ones known to the application programs and consist of the VPN and an offset within the virtual page. The physical addresses, which are the real addresses of the locations where the words of data are stored in external memory, consist of the PPN and an offset within the physical page for locating the addressed word of data. The TLB is updated in a privileged mode of operation, for example by an operating system (OS) program or by an application program in secure mode.
To protect the data stored in external memory, a two-level address translation technique has been described in document EP 1 522 923. This technique is illustrated in the diagram in FIG. 1 herein. A Memory Management Unit (MMU) consists of two cascading TLBs 31, 32, each one performing an address translation. The level one TLB, or upper TLB 31, receives a virtual address VA as input, and issues an intermediate address IA as output, which corresponds to the translation of the VA address stored in the upper TLB 31.
Functionally, the upper TLB 31 is used like a conventional TLB in traditional architectures. In other words, from the point of view of the application program, everything occurs as if there was only one TLB, and as if the intermediate address IA pointed directly to a page in physical memory. This is not the case. The MMU comprises a level two TLB, or lower TLB 32, which performs a second address translation. More specifically, the lower TBL 32 receives the intermediate address IA as input and issues a physical address PA as output, which actually points to a memory page in physical memory.
The upper TLB may be configured in a privileged mode of operation, for example by a program of the OS (supervisor mode). One may configure the lower TLB in an even more privileged mode of the processor only, for example in a privileged mode of the OS (secure supervisor mode). Thus, programs running on the processor outside of this more privileged mode do not have access to the physical addresses, which guarantees the inviolability and integrity of the data stored in external memory.
Other examples of two-level address translation are disclosed in document U.S. 2004/0143720. In it a processor with two distinct modes of operation is described: a secure mode (S) and a non-secure mode (NS). The first level of address translation (virtual to intermediate) is commanded by the S or NS modes, while the second level of address translation (intermediate to physical) is commanded by the NS mode only. A first embodiment is described, in which the processor only has one MMU and executes code (software) for merging page tables referencing two TLBs, one for each level of translation. In another described embodiment, the processor has a first and second cascading MMU, each with a TLB, for the first and second level of translation.
The two-level address translation technique offers great advantages. Yet it poses problems in performance and power consumption.
An ordinary CPU possesses a single level of address translation, meaning only one TLB. The operation of this hardware element is relatively slow and consumes power. The addition of a second cascading TLB has the effect of doubling the time necessary for translating a virtual address into a physical address, and also doubles the power consumption. These two consequences are difficult to accept in actual practice. Address translation is on the critical path when a user program is executed by a CPU. In addition, the TBL is one the parts of the CPU that consumes the most power (20% of the total power consumed by the CPU in certain cases).